---
title: "Training"
description: "Language-model work organized by continued pretraining, supervised fine-tuning and reasoning distillation, representation learning, preference optimization, and reinforcement learning."
---

## CPT (Continued Pretraining)

- [FreeV / FreeSet](https://arxiv.org/abs/2505.06096) (2025) — Continues pretraining Llama-3.1-8B on Verilog code filtered for licensing, deduplicated, and checked for syntax. [Data](https://huggingface.co/datasets/SETH-TAMU/FreeSet-V1.0-LabUse)

## SFT & Reasoning Distillation

- [AnalogSeeker](https://arxiv.org/abs/2508.10409) (2025) — Builds question-answer and reasoning data from analog circuit textbooks, then trains Qwen2.5-32B with KL-regularized SFT to improve circuit knowledge and reasoning. [Model](https://huggingface.co/analogllm/analog_model)
- [AST-guided SVRF Code Synthesis](https://arxiv.org/abs/2507.00352) (2025) — Siemens EDA applies AST-guided fine-tuning to T5 models and combines them with RAG to generate SVRF physical verification rules from natural language.
- [DeepRTL](https://github.com/PeterLau61/DeepRTL) (2025) — Uses curriculum-based instruction tuning of CodeT5+, progressing from lines and blocks to modules, to jointly learn Verilog understanding and generation. [Paper](https://arxiv.org/abs/2502.15832) [Data](https://huggingface.co/datasets/liuyi2000/deeprtl_finetuning_dataset)
- [IBM EDA Assistants with RAFT](https://research.ibm.com/publications/improving-llm-powered-eda-assistants-with-raft) (2025) — Uses synthetic EDA questions and answers for retrieval-augmented fine-tuning, with real questions guiding data generation to improve design documentation Q&A.
- [LaMAGIC2](https://proceedings.mlr.press/v267/chang25b.html) (2025) — Adapts pretrained Flan-T5-base with numerical inputs and circuit representations, then uses supervised fine-tuning to generate power converter topologies that meet specifications. [Code](https://github.com/turtleben/LaMAGIC)
- [ReasoningV](https://github.com/BUAA-CLab/ReasoningV) (2025) — First learns Verilog fundamentals with LoRA, then fully fine-tunes on simulation-tested code and associated reasoning traces, selecting a reasoning mode by problem difficulty. [Paper](https://arxiv.org/abs/2504.14560)
- [RF-Agent (RFIC)](https://github.com/Nina-nina123/RF-Agent) (2026) — Distills question-answer and reasoning data from RF textbooks, fine-tunes small Llama and Qwen language models, and compares RAG methods. [Paper](https://arxiv.org/abs/2607.18772)
- [ScaleRTL](https://arxiv.org/abs/2506.05566) (2025) — NVIDIA fine-tunes R1-Distill-Qwen-32B on long reasoning traces generated by DeepSeek-R1, then extends RTL reasoning through reflection and self-correction at inference time.
- [SiliconMind-V1](https://github.com/AS-SiliconMind/SiliconMind-V1) (2026) — Distills multi-agent generation and self-correction trajectories into Qwen, OLMo, and other models through two rounds of SFT for RTL generation and debugging. [Paper](https://arxiv.org/abs/2603.08719)
- [VeriThoughts](https://github.com/wilyub/VeriThoughts) (2025) — Builds training data using Verilog formal equivalence feedback and applies reasoning SFT to Qwen models. [Paper](https://arxiv.org/abs/2505.20302)

## Representation Learning & Knowledge Distillation

- [DeepRTL2](https://arxiv.org/abs/2506.15697) (2025) — Combines curriculum fine-tuning and contrastive learning on Llama and DeepSeek-Coder to support RTL generation, understanding, retrieval, and performance prediction with one model.
- [VeriDistill](https://ijcai.org/proceedings/2025/1033) (2025) — Huawei's Noah's Ark Lab freezes a code LLM, trains a lightweight QoR prediction head, and distills LUT graph network representations to incorporate low-level circuit information.

## Preference Optimization & RL

- [Alpha-RTL / TTT-RTL](https://arxiv.org/abs/2606.05253) (2026) — Updates model parameters at test time for each RTL design, combining tree search with syntax, simulation, and PPA rewards to optimize the implementation.
- [BUFFALO](https://research.nvidia.com/labs/electronic-design-automation/publication/lu2025buffalo/) (2025) — NVIDIA and Georgia Tech fine-tune pretrained T5-Large to jointly generate buffer tree structures and locations, then optimize PPA with net-level and full-chip GRPO. [Paper](https://gtcad.gatech.edu/www/papers/Hsiao-ICCAD25.pdf)
- [ChipMATE](https://github.com/zhongkaiyu/ChipMATE) (2026) — Trains separate Verilog and Python reference-model agents, then uses cross-verification-driven X-GRPO to learn multi-turn collaboration for RTL generation. [Paper](https://arxiv.org/abs/2605.12857)
- [ChipSeek](https://github.com/rong-hash/chipseek) (2026) — Starts with reasoning cold-start SFT, then uses CDPO reinforcement learning with simulation, synthesis, and PPA feedback to improve functional correctness and design quality. [Paper](https://aclanthology.org/2026.acl-long.1154/)
- [CodeV-R1 / QiMeng-CodeV-R1](https://github.com/IPRC-DIP/CodeV-R1) (2025) — Filters training data with automatically generated testbenches, distills reasoning capabilities, and applies adaptive DAPO to optimize Verilog generation. [Paper](https://arxiv.org/abs/2505.24183) [Data](https://huggingface.co/datasets/zhuyaoyu/CodeV-R1-dataset)
- [CovR](https://arxiv.org/abs/2609.19189) (2026) — Generates reasoning and stimulus data from coverage feedback, then applies SFT followed by GRPO to train models that generate high-coverage testbenches.
- [RTLSeek](https://arxiv.org/abs/2603.27630) (2026) — Follows SFT with staged GRPO training, using EDA feedback and AST diversity rewards to balance functional correctness with varied implementations.
- [VeriPrefer](https://github.com/CatIIIIIIII/VeriPrefer) (2025) — Converts testbench execution results into code preference pairs and applies DPO after SFT to improve the functional correctness of generated Verilog. [Paper](https://arxiv.org/abs/2504.15804) [Data](https://huggingface.co/datasets/LLM-EDA/pyra_tb)
- [VeriReason](https://github.com/NellyW8/VeriReason) (2025) — Follows reasoning SFT with GRPO using testbench and code-structure feedback to improve RTL generation and self-checking. [Paper](https://arxiv.org/abs/2505.11849) [Data](https://huggingface.co/collections/AI4EDA-CASE/verireason)
- [VeriRL](https://github.com/ZJU-OmniAI/VeriRL) (2025) — Alternates SFT and Reinforce++, trains reward models with testbench supervision, and improves RTL generation through trajectory rescoring and sample balancing. [Paper](https://arxiv.org/abs/2508.18462) [Data](https://huggingface.co/datasets/tttboy/Veribench-53K)