Awesome AI4Chip

We will continue building Awesome AI4Chip into the most comprehensive source of AI for Chip news and resources, collecting papers, open-source projects, datasets, benchmarks, tools, products, and technical articles. The goal is to help readers from different backgrounds quickly understand the field: identify key problems and technical approaches, find learning material and reproducible projects, and follow research and industry developments.

Where to Start

Background / Goal	Start with	Continue with
New to chip design; want to understand the flow and common software	EDA 101: design stages, tool interfaces, and key artifacts	Choose a path in the Guide
Familiar with LLMs; interested in RTL generation, domain post-training, or evaluation	LLMs for EDA: A Survey: tasks, model adaptation, data, and evaluation	AI Model: VerilogEval → CodeV-R1
RTL / EDA experience; want to build design agents	The Dawn of Agentic EDA: agent architectures, tool calls, and design feedback	AI EDA: OpenROAD flow → coding agent integration
Circuit fundamentals; interested in analog design and automation	JKU Analog Circuit Design: circuit design, simulation, and sizing	Analog / Mixed-Signal: ngspice batch simulation and parameter search
ML or computer architecture background; interested in model–accelerator co-design	MIT 6.5940: efficient models and hardware deployment	Chip for AI: Timeloop / Accelergy → Gemmini

Latest

• 2026-10-26 · Cadence Maestro — Introduces a family of domain models for chip and system design, trained with EDA tool feedback.
• 2026-10-22 · Back-to-the-Future (BTTF) — Updates its paper on RTL debugging with SQLite waveform data and natural-language queries.
• 2026-10-07 · RFChipAgent — Presents a multi-agent analog/RF design workflow connecting retrieval, topology selection and simulation-based optimization.
• 2026-10-04 · VHDL-REPOBENCH — Introduces repository-level VHDL evaluation focused on cross-file dependencies and hierarchical design understanding.
• 2026-10 · Build-A-Chip-Bench — Describes long-horizon evaluation from workload specifications to GDS, combining functional acceptance with PPA scoring.

Directory

• Guide
• AI Model
  • Data
  • Benchmark
  • Training
  • Harbor Environment Example
• EDA
  • EDA 101
  • Open Source
  • Closed Source
  • AI EDA
  • EDA Optimization
• Chip for AI
  • Hardware-aware ML
  • DSE (Design Space Exploration)
  • DSA (Domain-specific Architecture)
  • Kernel Optimization
• Surveys & Articles

Guide

AI Model

For readers familiar with LLMs who want to research RTL generation, domain post-training, or evaluation.

1. LLMs for EDA: A Survey — Covers EDA tasks, models, data, and evaluation, offering a quick overview of key directions at the intersection of LLMs and EDA.
2. VerilogEval — Follow the README’s spec-to-rtl workflow to understand evaluation from specifications through Verilog to simulation results.
3. CodeV-R1 — Use this Verilog post-training project to explore the training configurations in sft/, then the RL workflow and testbench reward in verl/. Compare these with the released data to understand how reasoning distillation and simulation feedback enter training.

If reading simple RTL is still difficult, begin with combinational and sequential logic exercises in HDLBits, then cocotb First Steps to connect Python testbenches with clocks, reset, assertions, and waveforms. Continue through Data, Benchmark, or Training for your research question.

AI EDA

For readers with RTL / EDA experience who want to build design agents or automated optimization flows.

1. The Dawn of Agentic EDA — Start with section 2 on agent architectures, then choose section 3 on RTL / Verification or section 4 on Physical Design.
2. OpenROAD Flow Scripts Tutorial — Use the Ibex / SKY130 example to understand the complete RTL-to-GDS flow.
3. OpenROAD — Running Claude Code in Docker — Connect a coding agent to a container with EDA tools and see how it accesses a project, builds, and runs tests.

For synthesis optimization, continue with Yosys Synthesis Starter to follow a FIFO from RTL to a netlist. For verification, use SymbiYosys Getting Started to learn assertions, bounded checks, proofs, and counterexamples. Find projects in AI EDA and EDA Optimization.

Analog / Mixed-Signal

Readers with circuit fundamentals who want an analog design and optimization environment can follow JKU Analog Circuit Design: chapters 1 and 2 introduce Xschem, ngspice, and an open PDK; chapter 3 covers gm/ID sizing; chapter 8 develops OTA simulation, PVT, and Monte Carlo analysis. The course includes circuit files and Python notebooks.

To connect simulation to parameter search or agents, continue with the looping, parameter modification, and data export sections of the ngspice Control Language Tutorial.

Chip for AI

For readers with machine learning or computer architecture foundations who want to study model–accelerator co-design.

1. MIT 6.5940 — TinyML and Efficient AI Computing — A foundation for studying hardware-aware ML.
2. Timeloop / Accelergy v4 and its exercises — Learn DSE without first implementing an RTL accelerator.

To study an accelerator’s hardware and software together, continue with Gemmini Quick Start: start with matrix multiplication in the simulator, then read Architecture for the systolic array, scratchpad, accumulator, and dataflow. Explore Hardware-aware ML, DSE, DSA, or Kernel Optimization for further work.

Contributors

Thanks to everyone helping maintain this directory. Contributions of new work, corrections to links and descriptions, and executable environments are welcome.

Community & Contact

Star the repository, share it with colleagues, or open a pull request to add work and improve the content. Suggestions are also welcome through Issues.

• Email: dengjiaji@foxnmail.com
• Personal GitHub: Dengjiaji
• WeChat: dengjiajicarl. Please include your institution, name, and reason for connecting.

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