Data

RTL Corpora and Synthetic Data

• CircuitWeave (2026) — Uses structured circuit contracts to combine synthetic schematic topologies with textual behavioral specifications, providing executable RTL generation data. Data
• DeepCircuitX (2025) — Provides RTL and multilevel annotations at repository, file, module, and block scales, linked to synthesized netlists and PPA data. Paper
• hdl2v (2025) — Translates or compiles VHDL, Chisel, and PyMTL3 into Verilog to expand human-written HDL training corpora. Data
• PyraNet (2025) — Provides hierarchical Verilog data with descriptions, compilation information, complexity measures, and quality rankings. Paper
• VerilogDB (2025) — Builds a structured RTL training database through syntax and synthesizability checks and module metadata extraction.

Netlist, Schematic, and Physical Design Data

• CircuitNet (1.0–3.0) (2022–2026) — Provides multimodal design data for congestion, DRC, IR drop, timing, and RTL-to-layout learning. Code Data
• Masala-CHAI (2024–2026) — Converts analog schematics into SPICE netlists and datasets using multimodal models, component detection, and verification.
• Netlistify (2025) — NYCU and NVIDIA jointly identify devices, orientations, and connections to convert schematics into SPICE netlists, with synthetic images and pretrained models. Paper

Data Interfaces and Metric Formats

• CircuitOps (2023) — Unifies circuit intermediate representations through relational tables and property graphs, connecting EDA data export, ML dataset construction, and deployment.
• METRICS2.1 / Metrics4ML (2021) — Defines JSON naming conventions and hierarchies for RTL-to-GDS metrics, with traceable experimental data.