EDA23 resources
Open Source
Digital design, analog simulation, physical implementation tools, and open PDKs.
Tools for executing designs, generating feedback, and reproducing experiments, including conventional EDA tools and open process environments.
Digital Design and Verification
- ABC — An open logic synthesis and formal verification system, widely used as an execution backend for learning-based synthesis optimization.
- cocotb — Runs Python testbenches with HDL simulators, supporting executable tasks and verification feedback.
- GEM (2025) — NVIDIA synthesizes RTL into AIGs and maps them to GPU Boolean computation structures to accelerate logic simulation.
- Icarus Verilog — An open-source Verilog compiler and simulator used as the execution backend for multiple RTL generation benchmarks.
- INSTA (2025) — NVIDIA’s GPU statistical static timing analysis tool provides differentiable timing gradients for gate sizing and other physical design optimization. Paper
- LibreLane — An extensible Python RTL-to-GDS flow based on OpenLane 2 that preserves configuration and design state at each step.
- OpenROAD / OpenROAD-flow-scripts — Open physical design tools and RTL-to-GDS flows that provide execution environments and PPA feedback for agents. Flows and Examples
- OpenSTA — Reads gate-level netlists, Liberty libraries, SDC constraints, and parasitics to perform static timing analysis and produce timing reports.
- SymbiYosys — Organizes bounded and unbounded property checking, coverage, and liveness verification for Yosys formal verification flows.
- Verilator — Compiles Verilog/SystemVerilog into C++/SystemC simulation models, providing lint, simulation, and coverage feedback.
- Yosys — An open RTL synthesis framework for synthesizability checks, netlist generation, and synthesis feedback for agents.
Analog Simulation and Layout
- ALIGN — Converts SPICE netlists and analog layout constraints into hierarchical layouts and GDSII.
- GLayout (2024) — Provides Python interfaces for circuit and layout generation across PDKs, with natural-language-to-layout and verification workflows.
- KLayout — Provides layout viewing, scripted generation, and DRC/LVS checks, connecting design artifacts with geometric verification.
- Magic — A VLSI layout editor with design rule checking, netlist extraction, and parasitic extraction.
- MAGICAL — Automatically generates constraints, placement, and routing from analog netlists to produce GDSII.
- Netgen — Compares layout-extracted and schematic netlists for LVS, checking devices, connectivity, and parameters.
- ngspice — A scriptable SPICE and mixed-signal simulator that supplies electrical feedback for circuit generation and sizing.
- Xschem — A hierarchical schematic editor and netlister that generates SPICE, Verilog, and VHDL netlists for circuit simulation workflows.
Integrated Environments and PDKs
- GF180MCU (2022) — An open PDK for GlobalFoundries’ 180nm MCU process, supporting analog and digital toolchains. This original Google repository is archived.
- IHP Open PDK / SG13G2 — An open 130nm BiCMOS PDK for analog, mixed-signal, and RF design.
- IIC-OSIC-TOOLS — Packages open-source analog and digital EDA tools and multiple open PDKs in a Docker environment.
- SKY130 — An open SkyWater 130nm process design kit with device models and technology data for analog and digital experiments.