Overview
Latest
Recent AI for Chip work and project updates, ordered by the original publication or revision date.
- 2026-10-26 · Cadence Maestro — Introduces a family of domain models for chip and system design, trained with EDA tool feedback.
- 2026-10-22 · Back-to-the-Future (BTTF) — Updates its paper on RTL debugging with SQLite waveform data and natural-language queries.
- 2026-10-07 · RFChipAgent — Presents a multi-agent analog/RF design workflow connecting retrieval, topology selection and simulation-based optimization.
- 2026-10-04 · VHDL-REPOBENCH — Introduces repository-level VHDL evaluation focused on cross-file dependencies and hierarchical design understanding.
- 2026-10 · Build-A-Chip-Bench — Describes long-horizon evaluation from workload specifications to GDS, combining functional acceptance with PPA scoring.