AI Model23 resources
Training
Language-model work organized by continued pretraining, supervised fine-tuning and reasoning distillation, representation learning, preference optimization, and reinforcement learning.
CPT (Continued Pretraining)
- FreeV / FreeSet (2025) — Continues pretraining Llama-3.1-8B on Verilog code filtered for licensing, deduplicated, and checked for syntax. Data
SFT & Reasoning Distillation
- AnalogSeeker (2025) — Builds question-answer and reasoning data from analog circuit textbooks, then trains Qwen2.5-32B with KL-regularized SFT to improve circuit knowledge and reasoning. Model
- AST-guided SVRF Code Synthesis (2025) — Siemens EDA applies AST-guided fine-tuning to T5 models and combines them with RAG to generate SVRF physical verification rules from natural language.
- DeepRTL (2025) — Uses curriculum-based instruction tuning of CodeT5+, progressing from lines and blocks to modules, to jointly learn Verilog understanding and generation. Paper Data
- IBM EDA Assistants with RAFT (2025) — Uses synthetic EDA questions and answers for retrieval-augmented fine-tuning, with real questions guiding data generation to improve design documentation Q&A.
- LaMAGIC2 (2025) — Adapts pretrained Flan-T5-base with numerical inputs and circuit representations, then uses supervised fine-tuning to generate power converter topologies that meet specifications. Code
- ReasoningV (2025) — First learns Verilog fundamentals with LoRA, then fully fine-tunes on simulation-tested code and associated reasoning traces, selecting a reasoning mode by problem difficulty. Paper
- RF-Agent (RFIC) (2026) — Distills question-answer and reasoning data from RF textbooks, fine-tunes small Llama and Qwen language models, and compares RAG methods. Paper
- ScaleRTL (2025) — NVIDIA fine-tunes R1-Distill-Qwen-32B on long reasoning traces generated by DeepSeek-R1, then extends RTL reasoning through reflection and self-correction at inference time.
- SiliconMind-V1 (2026) — Distills multi-agent generation and self-correction trajectories into Qwen, OLMo, and other models through two rounds of SFT for RTL generation and debugging. Paper
- VeriThoughts (2025) — Builds training data using Verilog formal equivalence feedback and applies reasoning SFT to Qwen models. Paper
Representation Learning & Knowledge Distillation
- DeepRTL2 (2025) — Combines curriculum fine-tuning and contrastive learning on Llama and DeepSeek-Coder to support RTL generation, understanding, retrieval, and performance prediction with one model.
- VeriDistill (2025) — Huawei’s Noah’s Ark Lab freezes a code LLM, trains a lightweight QoR prediction head, and distills LUT graph network representations to incorporate low-level circuit information.
Preference Optimization & RL
- Alpha-RTL / TTT-RTL (2026) — Updates model parameters at test time for each RTL design, combining tree search with syntax, simulation, and PPA rewards to optimize the implementation.
- BUFFALO (2025) — NVIDIA and Georgia Tech fine-tune pretrained T5-Large to jointly generate buffer tree structures and locations, then optimize PPA with net-level and full-chip GRPO. Paper
- ChipMATE (2026) — Trains separate Verilog and Python reference-model agents, then uses cross-verification-driven X-GRPO to learn multi-turn collaboration for RTL generation. Paper
- ChipSeek (2026) — Starts with reasoning cold-start SFT, then uses CDPO reinforcement learning with simulation, synthesis, and PPA feedback to improve functional correctness and design quality. Paper
- CodeV-R1 / QiMeng-CodeV-R1 (2025) — Filters training data with automatically generated testbenches, distills reasoning capabilities, and applies adaptive DAPO to optimize Verilog generation. Paper Data
- CovR (2026) — Generates reasoning and stimulus data from coverage feedback, then applies SFT followed by GRPO to train models that generate high-coverage testbenches.
- RTLSeek (2026) — Follows SFT with staged GRPO training, using EDA feedback and AST diversity rewards to balance functional correctness with varied implementations.
- VeriPrefer (2025) — Converts testbench execution results into code preference pairs and applies DPO after SFT to improve the functional correctness of generated Verilog. Paper Data
- VeriReason (2025) — Follows reasoning SFT with GRPO using testbench and code-structure feedback to improve RTL generation and self-checking. Paper Data
- VeriRL (2025) — Alternates SFT and Reinforce++, trains reward models with testbench supervision, and improves RTL generation through trajectory rescoring and sample balancing. Paper Data