Chip for AI12 resources
DSE (Design Space Exploration)
Search, simulation, and performance modeling for exploring accelerator architectures, mappings, and cluster configurations.
Search and Experiment Frameworks
- AlphaEvolve (2025–2026) — Combines LLMs, program evolution, and automated verification to optimize algorithms, with official examples in TPU arithmetic circuits, training kernels, and data-center scheduling. Follow-up Case Studies
- ArchGym (2023) — Unifies search-algorithm and architecture-simulator interfaces for ML-driven design-space exploration and experimental data collection. Paper
- CHIA (2026) — Uses workflow graphs and an extensible runtime for AI-driven hardware/software co-design experiments, with examples covering RTL, gem5 alignment, microarchitecture implementation, and critical-path optimization. Paper
Architecture and Mapping Evaluation
- Accel-Sim — Combines trace-driven simulation and hardware validation for programmable accelerators such as GPUs, with power modeling for architecture and AI workload research.
- GenZ (2024) — Analyzes compute, memory, and communication requirements across LLM inference scenarios to explore relationships between model characteristics and platform design parameters. Paper
- LLMCompass (2024) — Evaluates LLM inference platforms using execution, hardware mapping, and area-cost models, supporting chip-parameter and system-configuration exploration. Paper
- MAESTRO — Uses dataflow and tiling descriptions to analyze data reuse, performance, and hardware costs in DNN accelerators.
- SCALE-Sim v3 (2025) — Performs cycle-level simulation for a specified network and systolic-array configuration, producing timing, memory-bandwidth, and access traces. v3 Paper
- Timeloop / Accelergy — Explores tensor-accelerator design spaces through workload, architecture, and mapping descriptions, estimating performance, data movement, energy, and area. Code Related Code Format
- ZigZag — Jointly explores DNN accelerator memory hierarchies, spatial and temporal mappings, energy, and latency, with extensions for compute-in-memory. Paper
Clusters and Workloads
- ASTRA-sim — Jointly simulates distributed AI workload scheduling, collective communication, and compute/memory/network architectures for multilevel system design exploration. Follow-up Paper
- MLCommons Chakra — Represents AI workload computation, memory access, communication, and dependencies as open execution graphs, with trace conversion, generation, and simulation integration tools. Format and Tool Guide Updated Paper