AI EDA

AI EDA connects models to chip design and verification through tool use, design context and iterative feedback. This page covers design agents, long-running workflows, and the harnesses used to execute and evaluate them. For commercial products and platforms, see AI EDA Platforms in Closed Source.

RTL, HLS, and FPGA Design

• ACE-RTL (2026) — NVIDIA uses generation, reflection, and coordination roles to maintain iterative context, combining simulation feedback with RTL generation, verification, and repair. Paper Nemotron RTL Case Study
• AHRR (2026) — Combines agent-driven HLS with refinement of the compiled RTL to compare how abstraction levels affect hardware design efficiency. Paper
• AMD Ross (2026) — AMD’s FPGA/SoC agent skills and examples connect to Vivado through MCP, covering RTL simulation, timing analysis, HLS optimization, and on-board debugging. MCP and Tool Downloads
• Spec2RTL-Agent (2025) — NVIDIA, Cadence, and Georgia Tech decompose complex specifications into implementation plans, use multiple agents to generate and repair synthesizable C++, and convert it to RTL through HLS.

Verification, Debugging, and Design Data Queries

• Back-to-the-Future (BTTF) (2026) — Stores simulation waveforms in SQLite so agents can query signals in natural language and correlate them with versioned RTL.
• ChipXplore (2025) — Organizes PDK libraries and physical design data into SQL and graph databases for natural-language queries and exploration.
• RTLExplain (2025) — IBM builds structured knowledge bases for medium-to-large RTL projects, using RAG for code summaries, documentation generation, and design Q&A.
• UCAgent (2026) — Organizes RTL verification through staged checks and a Python verification toolchain, connecting Picker, Toffee, and language models. Paper

Analog and RF Design

• AnalogAgent (2026) — Uses separate roles for code generation, design optimization, and knowledge organization, with evolving memory to reuse analog design feedback.
• AnalogCoder (2025) — Designs analog circuits through Python/PySpice code generation, simulation feedback, and a subcircuit library. Data
• AnalogCoder-Pro (2026) — Combines circuit generation, waveform-image diagnosis, and parameter optimization to jointly explore analog topologies and device sizes. Data
• HeaRT (2025) — Uses hierarchical circuit reasoning trees to organize subcircuit and feedback-loop identification, and to adapt designs when specifications change.
• RFChipAgent (2026) — Connects retrieval, topology selection, schematic construction, and sizing under human supervision, using analog/RF simulation feedback to guide multiple agents.
• White-Box Reasoning (2025) — Grounds LLM reasoning about analog design in device data from gm/Id lookup tables, demonstrated on a two-stage operational amplifier.

Tool Orchestration, Evaluation, and Cross-Task Memory

• ChipMEM (2026) — Stores experience checked by synthesis, simulation, or formal verification as cross-task memory to guide later tool selection and execution.
• Design Conductor / VerCore (2026) — Generates RISC-V RTL from specifications, verifies it, and produces GDS using ASAP7 technology models to explore long-running agent design workflows. Follow-up FPGA Case Study
• Harbor — Organizes agent evaluation around task instructions, container environments, reference solutions, and graders, supporting separate verifier environments and trajectory collection. Task Format
• HORIZON (2026) — Uses Markdown to describe design tasks, evaluation methods, and acceptance criteria, guiding agents through iterative development in Git repositories.
• JARVIS (2025) — NVIDIA fine-tunes ChipNeMo on synthetic EDA scripts, then combines API-graph checks, rules, retrieval, and multi-agent repair to generate tool scripts.
• MCP4EDA (2025) — Orchestrates open-source RTL-to-GDS tools through MCP and optimizes synthesis scripts using post-place-and-route PPA feedback.
• OpenROAD-MCP (2026) — Provides agents with persistent OpenROAD sessions, command execution, historical metrics, and access to ORFS report plots.
• TuRTLe (2025) — Unifies multiple RTL benchmarks and EDA tools, covering syntax, functionality, equivalence, synthesis, PPA, and code-completion metrics. Paper