EDA Optimization

Covers circuit representation and performance prediction, RTL and logic optimization, physical design, and analog circuit design, using representation learning, reinforcement learning, search, and differentiable optimization.

Circuit Representation & Performance Prediction

• DeepGate4 (2025) — Combines a GNN encoder with a sparse graph Transformer, using gate-level and graph-level multitask supervision to learn functional and structural representations of large AIGs. Paper
• Multimodal Thermal Solver for 3DICs (2025) — UMD and Synopsys combine block-level thermal response learning, multimodal mapping, and linear superposition to predict thermal fields across chip sizes and power distributions. Technical Talk
• Pieceformer (2025) — Georgia Tech and Cadence combine message passing, partitioned graph Transformers, and contrastive self-supervision to measure netlist similarity and reuse partitioning experience.
• TRACE (2026) — Encodes RTL and netlists with a Transformer that follows logical levels, learning circuit representations through function-shift prediction and contrastive learning. Paper Data

RTL & Logic Optimization

• ASPEN (2025) — Cornell, NVIDIA, and UMD use LLMs to propose and select e-graph rewrite rules, then use PPA feedback to search for functionally equivalent RTL datapaths. Paper
• SynAct (2026) — Reads live synthesis reports and tool knowledge to select commands in a feedback loop and optimize timing and PPA.

Physical Design Optimization

• AlphaChip / Circuit Training — Uses distributed deep reinforcement learning for chip macro placement, with an open training framework and checkpoints.
• C3PO (2026) — NVIDIA jointly optimizes timing, routability, and wirelength with GPU-based differentiable optimization, adjusting objective weights during placement iterations. Paper
• CROP (2025) — Duke and Synopsys turn hierarchical RTL summaries into design vectors, retrieve parameter settings from similar circuits, and use RAG and LLMs to guide EDA flow tuning.
• DREAMPlace — Uses deep learning frameworks and GPUs to accelerate global and detailed placement, providing infrastructure for learning-based physical design.
• LEGO-Size (2025) — NVIDIA pretrains a specialized Transformer on library-cell sequences with self-supervision, follows with supervised learning, and uses GPU-based differentiable timing analysis to optimize gate sizes. Paper
• OpenROAD AutoTuner — Tunes RTL-to-GDS flow parameters through distributed hyperparameter search and collects PPA metrics.

Analog Circuit Design

• AnalogGenie (2025) — Represents circuits as device-pin sequences and trains an approximately 12M-parameter autoregressive Transformer from scratch to generate analog circuit topologies. Paper Data
• AstRL (2026) — Uses a graph neural network as a transistor-topology policy, combining expert behavior cloning, PPO, and simulation feedback to generate analog and mixed-signal circuits.